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ISLA224P
Timing Diagrams (Continued)
INP
INN
t A
CLKN
CLKP
CLKOUT
t CPD
t DC
t PD
LATENCY = L CYCLES
A DATA
B DATA
A DATA
B DATA
B DATA
A DATA
B DATA
D[13:0]
N-L
N-L
N-L+1
N-L+1
N-1
N
N
FIGURE 4. CMOS
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITION
(Note 5)
TYP
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
RMS Aperture Jitter
t A
j A
114
75
ps
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
Input Clock to Data Propagation Delay
Output Clock to Data Propagation Delay,
LVDS Mode
Output Clock to Data Propagation Delay,
CMOS Mode
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
t CPD
t CPD
dt CPD
t PD
t DC
t DC
t RSTS
AVDD, OVDD = 1.7V to 1.9V,
T A = -40°C to +85°C
AVDD, OVDD = 1.8V, T A = +25°C
AVDD, OVDD = 1.7V to 1.9V,
T A = -40°C to +85°C
Rising/Falling Edge
Rising/Falling Edge
1.65
1.9
-450
1.65
-0.1
-0.1
0.4
2.4
2.3
2.4
0.16
0.2
0.06
3
2.75
450
3.5
0.5
0.65
ns
ns
ps
ns
ns
ns
ns
CLKP)
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
t RSTH
0.02
0.35
ns
Synchronous Clock Divider Reset Recovery
Time
Latency (Pipeline Delay)
t RSTRT
L
DLL recovery time after
Synchronous Reset
52
10
μs
cycles
12
FN7570.1
November 30, 2012
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